In flash EEPROM (Electrically Erasable Programmable Read Only Memory) devices, the level of voltage required to transfer charge to or from a floating gate electrode through insulating layers to accomplish write and erase operation is critical to the successful operation of flash EEPROM devices. For example, reducing a required voltage necessary for erase operations would be advantageous in terms of power requirements and design constraints including critical dimensions of a flash EEPROM device.
It is known that the profile of gate structures can affect the hot electron injection processes or Fowler-Nordheim tunneling processes. An unacceptable gate profile may adversely affect the stability of a floating gate structure thereby adversely affecting the reliability of write and erase operations. For example, the electric field strength present at a polysilicon gate electrode/insulator interface determines the desired flow of current in response to applied voltages to accomplish write and erase operations.
In certain flash EEPROM structures, for example employing a floating gate and self-aligned control gate in a split gate FET configuration, a consistent and predictable profile of the gate structure is critical to proper electrical functioning of the device. As design rules have decreased to below about 0.25 micron technology, forming acceptable control and floating gate electrode profiles to accomplish write and erase operations has become increasingly difficult, with increasingly narrow process margins.
There is therefore a continuing need in the EEPROM device processing art to develop improved EEPROM devices and methods for forming the same to achieve improve device performance and reliability as well as improving process margins to enable scaled down memory cell size.
It is therefore an object of the invention to provide improved EEPROM devices and methods for forming the same to achieve improve device performance and reliability as well as improving process margins to enable scaled down memory cell size.